Non-volatile memories, such as flash memory devices, have supported the increased portability of consumer electronics, and have been utilized in relatively low power enterprise storage systems suitable for cloud computing and mass storage. The ever-present demand for almost continual advancement in these areas is often accompanied by demand to improve data storage capacity. The demand for greater storage capacity in turn stokes demand for greater storage density, so that specifications such as power consumption and form factor may be maintained and preferably reduced. As such, there is ongoing pressure to increase the storage density of non-volatile memories in order to further improve the useful attributes of such devices. However, a drawback of increasing storage density is that the stored data is increasingly prone to storage and/or reading errors.
Error control coding has been used to limit the increased likelihood of errors in memory systems. One error control coding option is known as concatenated coding. Concatenated coding is particularly promising because the generated codewords may be iteratively decoded, which in turn, may improve the error correction capability of the system. A concatenated coding scheme typically includes two data encoders separated by an interleaver. The interleaver shuffles data so that the two encoders receive the data in different orders from one another. Reciprocally, decoding employs two decoders separated by a de-interleaver that reverses the shuffling of the encoder-side interleaver. The shuffling and reverse-shuffling help to normalize the distribution of errors by de-clustering clustered errors. A normalized error distribution is often desirable because a normalized distribution enables the use of lower complexity codes and/or decoding processes.
However, various challenges, arising from the current reliance on interleaving, have curtailed the utilization of concatenated codes. For example, the complex circuitry needed to implement an interleaver and de-interleaver is generally power intensive and occupies a substantially large die area in monolithic implementations. Moreover, the architecture of a digital storage system that employs interleaving is typically designed to accommodate multi-bit symbol interleaving. For flash memory devices, multi-bit symbol interleaving typically utilizes byte wide channels across multiple ports. If the ports are controlled by independent controllers, the complexity of synchronizing the ports becomes a restriction on system implementation. Additionally, the use of interleaving restricts feeding forward corrected information from one decoder to another when a portion of a codeword is relatively easy to correct. The previously unattainable ability to feed forward corrected information would improve the ability to correct codewords having non-uniform error distributions. So even though concatenated coding may be capable of providing improved error correction capability, the use of concatenated codes that rely on interleaving is somewhat undesirable due to these and other physical constraints.